Vertical III-V Nanowire Tunnel Field-Effect Transistor

In this thesis fabrication and optimization of vertical III-V Tunneling Field-Effect transistors was explored. Usage of vertical nanowires, allows for combination of materials with large lattice mismatch in the same nanowire structure. TFETs in this thesis were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material quality. Usage of these material systems allowed for fabrication of devices with staggered and broken band-gap alignment. To fully harvest the benefits from these structures, the fabrication process was optimized. This was performed by exploring different spacer and gate technologies, required for vertical devices. Furthermore, improvement of electrostatics was achieved by reduction of the channel diameter and high-κ interface. Further improvements of the performance were achieved by scaling of the device dimensions such as nanowire lengths, spacer thickness, and gate-length. Used fabrication techniques allowed us to fabricate devices with a channel diameter of 11 nm. By switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, which allowed us to fabricate devices with record performance, reaching a minimum subthreshold swing of 48 mV/decade and a record high I60 of 0.31 μA/μm at a drive voltage of 0.3 V. Stability of the process allowed us to demonstrate data from a large number of TFETs with ability to operate below the thermal limit of 60 mV/decade. This allowed us to study correlations between important device parameter such as: I60, on-current, subthreshold swing, and off-current. Using transmission electron microscopy, the heterojunction was characterized. Furthermore, TCAD modeling was performed to understand what limits the performance of these devices. Also, electrical measurement of the random telegraph noise allowed us to understand the impact the oxide defects have on highly scaled devices

Thin electron beam defined hydrogen silsesquioxane spacers for vertical nanowire transistors

A method to fabricate inorganic vertical spacer layers with well-controlled thickness down to 40 nm using electron beam exposure is demonstrated. These spacers are suitable in vertical nanowire transistor configuration. As spacer material, the authors use hydrogen silsesquioxane (HSQ), a material with low permittivity and high durability. They show that the resulting HSQ thickness can be controlled by electron dose used and it also depend on the initial thickness of the HSQ layer. To achieve good reproducibility, the authors found it necessary to fully submerge the nanowires beneath the HSQ layer initially and that the thickness of HSQ before exposure needs to be determined. Finally, they introduce these steps in an existing transistor process and demonstrate vertical nanowire transistors with high performance. (C) 2014 American Vacuum Society

InAs/GaSb vertical nanowire TFETs on Si for digital and analogue applications

Vertical InAs/GaSb nanowire TFETs with diameters of 20 nm and 25 nm have been fabricated and characterized. The influence of diameter, gate-placement, and nanowire numbers have been studied. The best device shows a subthreshold swing of 68 mV/dec at VDS = 0.3 V and 26 μA/μm at VDS = 0.3 V and VGS = 0.5 V. It achieves a self-gain larger than 100 with high transconductance efficiency

Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade

We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability to reach a point subthreshold swing of 35 mV/decade at VDS = 0.05 V. Furthermore, the impact of drain, channel and source diameter scaling on the subthreshold swing and currents are studied. Impact of gate-overlap is more evident for devices with highly scaled source due to strong reduction of the current. Furthermore, small channel diameter makes these devices more susceptible to Random Telegraph Signal noise

Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si

We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field-effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at VDS=0.3 V, was achieved for a device with 20-nm InAs diamter. The on-current for the same device was 35 µA/µm at VGS=0.5 V and VDS=0.5 V. The fabrication technique used allows downscaling of the InAs diameter down to 11 nm with a flexible gate placement

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire Tunnel Field-Effect Transistors

In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire Tunnel Field-Effect Transistors to study influence of the source doping on their performance. Overall, the doping level impacts both off-state and on-state performance of these devices. Separation of the doping from the heterostructure improved the subthreshod swing of the devices. Best devices reached a point subthreshold swing of 30 mV/dec at 100x higher currents than what Si-based TFETs has achieved previously. However, separation of doping from the heterostructure had a significant impact on the on-state performance of these devices due to effects related to source depletion. Increase of the doping level, helped to improve the on-state performance, which also increased the subthreshold swing. Thus, further optimization of doping incorporation at the heterostructure will help to improve vertical InAs/InGaAsSb/GaSb nanowire TFETs

RF Characterization of Vertical InAs Nanowire MOSFETs with f(t) and f(max) above 140 GHz

We present RF characterization of vertical gateall- around InAs nanowire MOSFETs integrated on Si substrates with peak f(t) = 142 GHz and f(max) = 155 GHz, representing the record for vertical nanowire transistors. The devices has an L-g approximate to 150 nm with a g(m)=700 mS/mm for a nanowire diameter of 38 nm and an EOT = 1.4 nm. The high values of f(t) is achieved through electron beam lithography patterning of the gate and drain contact which substantially decreases the parasitic capacitances through reduction of the overlay capacitance, which is in good agreement with TCAD modeling

Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation set-up. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation set-up is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found